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4.5 RON, Triple/Quad SPDT 5 V, +12 V, +5 V, and +3.3 V Switches ADG1633/ADG1634
FEATURES
4.5 typical on resistance 1 on-resistance flatness Up to 206 mA continuous current 3.3 V to 8 V dual-supply operation 3.3 V to 16 V single-supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation ADG1633 16-lead TSSOP and 16-lead, 3 mm x 3 mm LFCSP ADG1634 20-lead TSSOP and 20-lead, 4 mm x 4 mm LFCSP
FUNCTIONAL BLOCK DIAGRAMS
ADG1633
S1A D1 S1B S3B D3 S2B D2 S2A LOGIC S3A
IN1 IN2 IN3 EN SWITCHES SHOWN FOR A 1 INPUT LOGIC.
08319-001
APPLICATIONS
Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements
Figure 1. ADG1633 TSSOP and LFCSP_VQ
ADG1634
S1A D1 S1B IN1 IN2 S2B D2 S2A S4A D4 S4B IN4 IN3 S3B D3 S3A
GENERAL DESCRIPTION
The ADG1633 and ADG1634 are monolithic industrial CMOS (iCMOS(R)) analog switches comprising three independently selectable single-pole, double-throw (SPDT) switches and four independently selectable SPDT switches, respectively. All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input on the ADG1633 (LFCSP and TSSOP packages) and ADG1634 (LFCSP package only) is used to enable or disable the devices. When disabled, all channels are switched off. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.
SWITCHES SHOWN FOR A 1 INPUT LOGIC.
Figure 2. ADG1634 TSSOP
ADG1634
S1A D1 S1B S2B D2 S2A LOGIC S4A D4 S4B S3B D3 S3A
SWITCHES SHOWN FOR A 1 INPUT LOGIC.
Figure 3. ADG1634 LFCSP_VQ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08319-003
IN1 IN2 IN3 IN4 EN
08319-002
ADG1633/ADG1634 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Dual Supply ......................................................................... 3 12 V Single Supply ........................................................................ 4 5 V Single Supply .......................................................................... 5 3.3 V Single Supply ....................................................................... 6 Continuous Current per Channel, S or D ..................................7 Absolute Maximum Ratings ............................................................8 ESD Caution...................................................................................8 Pin Configurations and Function Descriptions ............................9 Typical Performance Characteristics ........................................... 11 Test Circuits ..................................................................................... 14 Terminology .................................................................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 19
REVISION HISTORY
7/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG1633/ADG1634 SPECIFICATIONS
5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD/VSS
1
25C
-40C to +85C
-40C to +125C VDD to VSS
Unit V typ max typ max typ max nA typ
Test Conditions/Comments
4.5 5 0.12 0.25 1 1.3 0.01 0.1 0.02 0.15 0.02 0.15
7 0.3 1.7
8 0.35 2
VS = 4.5 V, IS = -10 mA; see Figure 26 VDD = 4.5 V, VSS = 4.5 V VS = 4.5 V, IS = -10 mA VS = 4.5 V, IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; see Figure 27 VS = 4.5V, VD = 4.5 V; see Figure 27 VS = VD = 4.5 V; see Figure 28
1.5 2 2
12 20 20 2.0 0.8
nA max nA typ nA max nA typ nA max V min V max nA typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max V min/max
1 0.1 8 161 200 61 79 162 199 44 -12.5 -64 -64 0.3 103 19 33 57 0.001 1.0 3.3/8
VIN = VGND or VDD
236 88 232
264 98 259 30
RL = 300 , CL = 35 pF VS = 2.5 V; see Figure 29 RL = 300 , CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 , CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 , CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 30 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 110 , VS = 5 V p-p, f = 20 Hz to 20 kHz; see Figure 36 RL = 50 , CL = 5 pF; see Figure 34 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = -5.5 V Digital inputs = 0 V or VDD
Guaranteed by design, but not subject to production test. Rev. 0 | Page 3 of 20
ADG1633/ADG1634
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD TSSOP LFCSP VDD
1
25C
-40C to +85C
-40C to +125C 0 V to VDD
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max
Test Conditions/Comments
4 4.5 0.12 0.25 0.9 1.2 0.01 0.1 0.02 0.15 0.02 0.15
6.5 0.3 1.6
7.5 0.35 1.9
VS = 0 V to 10 V, IS = -10 mA; see Figure 26 VDD = 10.8 V, VSS = 0 V VS = 10 V, IS = -10 mA VS = 0 V to 10 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 VS = VD = 1 V or 10 V; see Figure 28
1.5 2 2
12 20 20 2.0 0.8
1 0.1 8 127 151 31 38 128 152 45
nA typ
A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max A typ A max A typ A max V min/max
VIN = VGND or VDD
182 43 180
205 47 200 30
-12.4
-64 -64 0.3 109 19 32 56 0.001 1.0 300 480 375 600 3.3/16
RL = 300 , CL = 35 pF VS = 8 V; see Figure 29 RL = 300 , CL = 35 pF VS = 8 V; see Figure 31 RL = 300 , CL = 35 pF VS = 8 V; see Figure 31 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 30 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 110 , VS = 5 V p-p, f = 20 Hz to 20 kHz; see Figure 36 RL = 50 , CL = 5 pF; see Figure 34 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 12 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V
Guaranteed by design, but not subject to production test.
Rev. 0 | Page 4 of 20
ADG1633/ADG1634
5 V SINGLE SUPPLY
VDD = 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD
1
25C
-40C to +85C
-40C to +125C 0 V to VDD
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max nA typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max V min/max
Test Conditions/Comments
8.5 10 0.15 0.3 1.7 2.3 0.01 0.1 0.02 0.15 0.02 0.15
12.5 0.35 2.7
14 0.4 3
VS = 0 V to 4.5 V, IS = -10 mA; see Figure 26 VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = -10 mA VS = 0 V to 4.5 V, IS = -10 mA VDD = 5.5 V, VSS = 0 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 27 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 27 VS = VD = 1 V or 4.5 V; see Figure 28
1.5 2 2
12 20 20 2.0 0.8
1 0.1 8 199 254 68 90 201 256 57 -5 -64 -64 0.27 104 21 37 62 0.001 1.0 3.3/16
VIN = VGND or VDD
303 102 300
337 110 333 37
RL = 300 , CL = 35 pF VS = 2.5 V; see Figure 29 RL = 300 , CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 , CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 , CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 30 VS = 2.5 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 33 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 35 RL = 110 , f = 20 Hz to 20 kHz, VS = 3.5 V p-p; see Figure 36 RL = 50 , CL = 5 pF; see Figure 34 VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VDD = 5.5 V Digital inputs = 0 V or VDD
Guaranteed by design, but not subject to production test.
Rev. 0 | Page 5 of 20
ADG1633/ADG1634
3.3 V SINGLE SUPPLY
VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) -3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD
1
25C
-40C to +85C
-40C to +125C 0 V to VDD 16.5 0.3 6.5
Unit V typ typ typ nA typ nA max nA typ nA max nA typ nA max V min V max nA typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max V min/max
Test Conditions/Comments
13.5 0.25 5 0.01 0.1 0.01 0.15 0.01 0.15
15 0.28 5.5
VS = 0 V to VDD, IS = -10 mA; see Figure 26, VDD = 3.3 V, VSS = 0 V VS = 0 V to VDD, IS = -10 mA VS = 0 V to VDD, IS = -10 mA VDD = 3.6 V, VSS = 0 V VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 27 VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 27 VS = VD = 0.6 V or 3 V; see Figure 28
1.5 2 2
12 20 20 2.0 0.8
1 0.1 8 309 429 132 184 313 416 81 -10 -64 -64 0.6 117 22 39 64 0.001 1.0 3.3/16
VIN = VGND or VDD
466 201 470
508 210 509 48
RL = 300 , CL = 35 pF VS = 1.5 V; see Figure 29 RL = 300 , CL = 35 pF VS = 1.5 V; see Figure 31 RL = 300 , CL = 35 pF VS = 1.5 V; see Figure 31 RL = 300 , CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 30 VS = 1.5 V, RS = 0 , CL = 1 nF; see Figure 32 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 33 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 35 RL = 110 , f = 20 Hz to 20 kHz, VS = 2 V p-p; see Figure 36 RL = 50 , CL = 5 pF; see Figure 34 VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VDD = 3.6 V Digital inputs = 0 V or VDD
Guaranteed by design, but not subject to production test.
Rev. 0 | Page 6 of 20
ADG1633/ADG1634
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5. ADG1633
Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = -5 V TSSOP (JA = 112.6C/W) LFCSP (JA = 48.7C/W) VDD = 12 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 48.7C/W) VDD = 5 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 48.7C/W) VDD = 3.3 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 48.7C/W) 25C 85C 125C Unit
126 206 133 213 98 157 77 129
84 126 87 133 70 105 56 87
56 70 56 73 45 63 38 56
mA max mA max mA max mA max mA max mA max mA max mA max
Table 6. ADG1634
Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = -5 V TSSOP (JA = 95C/W) LFCSP (JA = 30.4C/W) VDD = 12 V, VSS = 0 V TSSOP (JA = 95C/W) LFCSP (JA = 30.4C/W) VDD = 5 V, VSS = 0 V TSSOP (JA = 95C/W) LFCSP (JA = 30.4C/W) VDD = 3.3 V, VSS = 0 V TSSOP (JA = 95C/W) LFCSP (JA = 30.4C/W) 25C 85C 125C Unit
112 220 119 234 87 171 70 140
77 136 80 140 63 112 52 94
52 73 52 73 42 66 35 59
mA max mA max mA max mA max mA max mA max mA max mA max
Rev. 0 | Page 7 of 20
ADG1633/ADG1634 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 7.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D 2 Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance, 0 Airflow (4Layer Board) 20-Lead TSSOP, JA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP (3 mm x 3 mm), JA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP (4 mm x 4 mm), JA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb free
1
Rating 18 V -0.3 V to +18 V +0.3 V to -18 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 450 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% -40C to +125C -65C to +150C 150C 112.6C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
95C/W
48.7C/W
30.4C/W
260C
2
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. See Table 5 and Table 6.
Rev. 0 | Page 8 of 20
ADG1633/ADG1634 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
15 VDD 14 GND 16 S1A 13 IN1
VDD 1 S1A 2 D1 3 S1B 4 S2B
5
16 15 14
GND IN1 EN VSS S3B D3 S3A
08319-004
D1 1 S1B 2 S2B 3 D2 4
PIN 1 INDICATOR
12 EN 11 VSS 10 S3B 9 D3
ADG1633
TOP VIEW (Not to Scale)
ADG1633
TOP VIEW (Not to Scale)
13 12 11 10 9
S2A
7
S3A 8
S2A 5
IN3 7
IN2 6
D2 6
IN2 8
IN3
NOTES 1. EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS.
Figure 4. ADG1633 TSSOP Pin Configuration
Figure 5. ADG1633 LFCSP_VQ Pin Configuration
Table 8. ADG1633 Pin Function Descriptions
Pin No. TSSOP LFCSP_VQ 1 15 2 16 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 16 N/A 13 14 17 Mnemonic VDD S1A D1 S1B S2B D2 S2A IN2 IN3 S3A D3 S3B VSS EN IN1 GND EP Description Most Positive Power Supply Potential. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input 2. Logic Control Input 3. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Active Low Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low, INx logic inputs determine the on switches. Logic Control Input 1. Ground (0 V) Reference. Exposed Pad. The exposed pad is tied to the substrate, VSS.
Table 9. ADG1633 Truth Table
EN 1 0 0
1
INx X1 0 1
SxA Off Off On
SxB Off On Off
X = don't care.
Rev. 0 | Page 9 of 20
08319-005
ADG1633/ADG1634
IN1 1 S1A 2 D1 3 S1B 4 VSS 5 GND
6 20 19 18 17
IN4 S4A D4 S4B VDD NC S3B D3
D1 S1B VSS GND S2B 1 2 3 4 5
ADG1634
TOP VIEW (Not to Scale)
20 19 18 17 16
PIN 1 INDICATOR
S1A IN1 EN IN4 S4A
16 15 14 13 12 11
ADG1634
TOP VIEW (Not to Scale)
S2B 7 D2 8 S2A
9
15 14 13 12 11
D4 S4B VDD S3B D3
IN2 10
IN3
08319-006
D2 S2A IN2 IN3 S3A
6 7 8 9 10
S3A
NC = NO CONNECT
NOTES 1. EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS.
Figure 6. ADG1634 TSSOP Pin Configuration
Figure 7. ADG1634 LFCSP_VQ Pin Configuration
Table 10. ADG1634 Pin Function Descriptions
Pin No. TSSOP LFCSP_VQ 1 19 2 20 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 N/A 16 13 17 14 18 15 19 16 20 17 N/A 18 N/A 21 Mnemonic IN1 S1A D1 S1B VSS GND S2B D2 S2A IN2 IN3 S3A D3 S3B NC VDD S4B D4 S4A IN4 EN EP Description Logic Control Input 1. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Ground (0 V) Reference. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input 2. Logic Control Input 3. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. No Connect. Most Positive Power Supply Potential. Source Terminal 4B. Can be an input or an output. Drain Terminal 4. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Logic Control Input 4. Active Low Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low, INx logic inputs determine the on switches. Exposed Pad. The exposed pad is tied to the substrate, VSS.
Table 11. ADG1634 TSSOP Truth Table
INx 0 1 SxA Off On SxB On Off
Table 12. ADG1634 LFCSP_VQ Truth Table
EN 1 0 0
1
INx X1 0 1
SxA Off Off On
SxB Off On Off
X = don't care. Rev. 0 | Page 10 of 20
08319-007
ADG1633/ADG1634 TYPICAL PERFORMANCE CHARACTERISTICS
7 6 5 4 3 2 1 0 VDD = +3.3V VSS = -3.3V VDD = +5V VSS = -5V VDD = +8V VSS = -8V TA = 25C
7 6 5
VDD = 12V VSS = 0V
ON RESISTANCE ()
ON RESISTANCE ()
TA = +125C 4 3 2 1 0 TA = +85C TA = +25C TA = -40C
08319-029
-8
-6
-4
-2
0
2
4
6
8
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 8. On Resistance vs. VD (VS), Dual Supply
Figure 11. On Resistance vs. VD (VS) for Different Temperatures, 12 V Single Supply
12
16 14 12 VDD = 3.3V VSS = 0V TA = 25C
10
TA = +125C TA = +85C TA = +25C
ON RESISTANCE ()
ON RESISTANCE ()
10 8 6 4 2 0 VDD = 12V VSS = 0V VDD = 16V VSS = 0V VDD = 5V VSS = 0V
8
6
TA = -40C
4
2
VDD = 5V VSS = 0V
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
08319-033
08319-021
0
2
4
6
8
10
12
14
16
SOURCE OR DRAIN VOLTAGE (V)
08319-030
0
SOURCE OR DRAIN VOLTAGE (V)
Figure 9. On Resistance vs. VD (VS), Single Supply
Figure 12. On Resistance vs. VD (VS) for Different Temperatures, 5 V Single Supply
18 16 14 VDD = 3.3V VSS = 0V
7 6 5 4 TA = +25C 3 2 1 0 -5 TA = -40C TA = +125C TA = +85C
VDD = +5V VSS = -5V
ON RESISTANCE ()
ON RESISTANCE ()
12 10 8 6 4 2
TA = +125C TA = +85C TA = +25C TA = -40C
-4
-3
-2
-1
0
1
2
3
4
5
08319-031
0
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 10. On Resistance vs. VD (VS) for Different Temperatures, 5 V Dual Supply
Figure 13. On Resistance vs. VD (VS) for Different Temperatures, 3.3 V Single Supply
Rev. 0 | Page 11 of 20
08319-032
ADG1633/ADG1634
12 10 8 LEAKAGE CURRENT (nA) 6 4 2 0 -2 -4 -6 -8
0 20 40 60 ID, IS (ON) - - IS (OFF) - + ID (OFF) + - VDD = +5V VSS = -5V VBIAS = +4.5V/-4.5V
10
8
VDD = 3.3V VSS = 0V VBIAS = 0.6V/3V
LEAKAGE CURRENT (nA)
ID (OFF) - + ID, IS (ON) + + IS (OFF) + -
6
4
ID, IS (ON) + + ID, IS (ON) - - ID (OFF) - + IS (OFF) + - ID (OFF) + - IS (OFF) - +
2
0
08319-035
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 14. ADG1633 Leakage Currents vs. Temperature, 5 V Dual Supply
15
Figure 17. ADG1633 Leakage Currents vs. Temperature, 3.3 V Single Supply
600
VDD = 12V VSS = 0V VBIAS = 1V/10V ID, IS (ON) + + ID (OFF) - + IS (OFF) + -
IDD PER CHANNEL TA = 25C IDD = +12V ISS = 0V
10
500
LEAKAGE CURRENT (nA)
400
IDD (A)
5
300 IDD = +5V ISS = -5V IDD = +5V ISS = 0V 100 IDD = +3.3V ISS = 0V
0
200
-5 ID, IS (ON) - - IS (OFF) - + ID (OFF) + -
0
20
40
60
80
100
120
08319-034
0
2
4
6
8
10
12
14
TEMPERATURE (C)
LOGIC (V)
Figure 15. ADG1633 Leakage Currents vs. Temperature, 12 V Single Supply
10
VDD = 5V VSS = 0V VBIAS = 1V/4.5V
CHARGE INJECTION (pC)
Figure 18. IDD vs. Logic Level
100 80 60 40 20 0 -20 -40 -60 -80 -100 VDD = +5V VSS = -5V VDD = +3.3V VSS = 0V VDD = +5V VSS = 0V VDD = +12V VSS = 0V
8
LEAKAGE CURRENT (nA)
6
4
ID, IS (ON) + + ID (OFF) - + ID (OFF) + - IS (OFF) + - IS (OFF) - + ID, IS (ON) - -
2
0
TEMPERATURE (C)
VS (V)
Figure 16. ADG1633 Leakage Currents vs. Temperature, 5 V Single Supply
Figure 19. Charge Injection vs. Source Voltage
Rev. 0 | Page 12 of 20
08319-027
0
20
40
60
80
100
120
08319-036
-2
-120 -6
-4
-2
0
2
4
6
8
10
12
14
08319-020
-10
0
08319-019
-2
ADG1633/ADG1634
350 TA = 25C 300 250 200 150 100 50 0 -40 VDD = +3.3V, VSS = 0V VDD = +5V, VSS = 0V VDD = +5V, VSS = -5V VDD = +12V, VSS = 0V
0
-1
INSERTION LOSS (dB)
TA = 25C VDD = +5V VSS = -5V
TRANSITION TIME (ns)
-2
-3
-4
-5
-20
0
20
40
60
80
100
120
08319-025
100k
1M
10M
100M
1G
TEMPERATURE (C)
FREQUENCY (Hz)
Figure 20. Transition Time vs. Temperature
0 -10 -20
OFF ISOLATION (dB)
Figure 23. On Response vs. Frequency
0.7 0.6 0.5
TA = 25C VDD = +5V VSS = -5V
LOAD = 110 TA = 25C
VDD = +3.3V, VS = 2V p-p
-30
THD + N (%)
-40 -50 -60 -70 -80
08319-023
0.4 0.3 0.2 0.1 0
VDD = +5V, VS = 3.5V p-p
VDD = +5V, VSS = -5V, VS = 5V p-p VDD = +12V, VS = 5V p-p
0 5k 10k FREQUENCY (Hz) 15k 20k
08319-028 08319-026
-90 10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 21. Off Isolation vs. Frequency
Figure 24. THD + N vs. Frequency
0 -10 -20
0
TA = 25C VDD = +5V VSS = -5V
-20
TA = 25C VDD = +5V VSS = -5V NO DECOUPLING CAPACITORS
CROSSTALK (dB)
-40 -50 -60 -70 -80
08319-024
ACPSRR (dB)
-30
-40
-60
-80 DECOUPLING CAPACITORS
-100
-90 10k
100k
1M
10M
100M
1G
-120 1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Crosstalk vs. Frequency
Figure 25. ACPSRR vs. Frequency
Rev. 0 | Page 13 of 20
08319-022
-6 10k
ADG1633/ADG1634 TEST CIRCUITS
V
IS (OFF) A S D ID (OFF) A
08319-009
S
D IDS
08319-008
VS
VS
VD
Figure 26. On Resistance
ID (ON) NC S D A
08319-010
Figure 27. Off Leakage
NC = NO CONNECT
VD
Figure 28. On Leakage
0.1F
VDD
VSS
0.1F
VIN
50%
50%
VDD VS SB SA IN VIN GND
VSS D RL 100 CL 35pF VOUT VIN 50% 90% 50% 90%
VOUT
tOFF
Figure 29. Switching Timing
0.1F
VDD
VSS
0.1F VIN
VDD VS SB SA IN VIN GND
VSS D RL 100 CL 35pF VOUT
VOUT
80%
tBBM
tBBM
08319-012
Figure 30. Break-Before-Make Delay, tD
0.1F
VDD
VSS
0.1F 3V ENABLE DRIVE (VIN) VS 0V VOUT VOUT RL 100 CL 35pF OUTPUT 0V 0.9VOUT 50% 50%
VDD INx INx INx EN VIN 50 GND
VSS S1A S1B D1
ADG1633
tOFF (EN)
0.9VOUT
08319-013
tON (EN)
Figure 31. Enable Delay, tON (EN), tOFF (EN)
Rev. 0 | Page 14 of 20
08319-011
tON
ADG1633/ADG1634
0.1F VDD VSS 0.1F VIN (NORMALLY CLOSED SWITCH)
VDD VS D IN VIN GND
VSS SB SA CL 1nF NC VOUT
ON
OFF
VIN (NORMALLY OPEN SWITCH) VOUT VOUT
Figure 32. Charge Injection
08319-014
QINJ = CL x VOUT
VDD
VSS 0.1F
VDD 0.1F
VSS 0.1F NETWORK ANALYZER NC 50 VS
D
VS IN NETWORK ANALYZER VOUT RL 50
0.1F
VDD SA
VSS SB
VDD SA
VSS
50
D SB R 50
IN
VIN GND
RL 50
VOUT
GND
08319-015
OFF ISOLATION = 20 log
VOUT VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 33. Off Isolation
VDD 0.1F VSS 0.1F NETWORK ANALYZER NC 50 VDD VS
D
Figure 35. Channel-to-Channel Crosstalk
VDD 0.1F
VSS 0.1F AUDIO PRECISION VSS S RS VS V p-p D RL 110 VOUT
08319-018
VDD SA
VSS SB
IN
VIN GND
RL 50
VOUT
IN
VIN GND VOUT WITH SWITCH VOUT WITHOUT SWITCH
08319-016
INSERTION LOSS = 20 log
Figure 34. Bandwidth
Figure 36. THD + Noise
Rev. 0 | Page 15 of 20
08319-017
VOUT VS
ADG1633/ADG1634 TERMINOLOGY
RON Ohmic resistance between Terminal D and Terminal S. RON The difference between the RON of any two channels. RFLAT(ON) The difference between the maximum and minimum value of on resistance measured. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. ID, IS (On) Channel leakage current when the switch is on. VD (VS) Analog voltage on Terminal D and Terminal S. CS (Off) Channel input capacitance for off condition. CD (Off) Channel output capacitance for off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANS Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. tBBM Off time measured between the 80% point of both switches when switching from one address state to another. VIL Maximum input voltage for Logic 0. VIH Minimum input voltage for Logic 1. IIL (IIH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.
Rev. 0 | Page 16 of 20
ADG1633/ADG1634 OUTLINE DIMENSIONS
5.10 5.00 4.90
16 9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
PIN 1 INDICATOR
3.10 3.00 SQ 2.90 0.50 BSC
0.30 0.23 0.18
13 12 EXPOSED PAD 16 1
PIN 1 INDICATOR
1.75 1.60 SQ 1.55
4
9
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.50 0.40 0.30
8
5
BOTTOM VIEW
0.20 MIN
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm, Very VeryThin Quad (CP-16-22) Dimensions shown in millimeters
Rev. 0 | Page 17 of 20
070209-C
ADG1633/ADG1634
6.60 6.50 6.40
20
11
4.50 4.40 4.30 6.40 BSC
1 10
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 39. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX
0.60 MAX
15
16
20 1
PIN 1 INDICATOR
2.65 2.50 SQ 2.35
5
PIN 1 INDICATOR
3.75 BSC SQ
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
TOP VIEW 0.80 MAX 0.65 TYP
0.50 0.40 0.30
11
10
6
0.25 MIN
1.00 0.85 0.80 SEATING PLANE
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters
Rev. 0 | Page 18 of 20
090408-B
0.30 0.23 0.18
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
ADG1633/ADG1634
ORDERING GUIDE
Model ADG1633BRUZ 1 ADG1633BRUZ-REEL71 ADG1633BCPZ-REEL71 ADG1634BRUZ1 ADG1634BRUZ-REEL71 ADG1634BCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
EN Pin Yes Yes Yes No No Yes
Package Option RU-16 RU-16 CP-16-22 RU-20 RU-20 CP-20-4
Branding
S3D
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADG1633/ADG1634 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08319-0-7/09(0)
Rev. 0 | Page 20 of 20

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